1. Technical Field
The present invention relates in general to clock signal distribution within an integrated circuit and in particular, to a differential clock signal distribution system. Still more particularly, the present invention relates to a differential clock signal distribution network utilizing negative impedance terminations.
2. Description of the Related Art
Synchronization of logic circuits within an integrated circuit is accomplished by distributing a master clock signal to each timing critical circuit. The proper operation of an information processing unit, such as a microprocessor, requires that all digital signals are in a steady state when data is clocked. In all "clocked" systems there is a master clock which controls the transfer of data.
An oscillator and a central buffer are typically utilized in an integrated circuit to produce and amplify a clock signal for distribution to digital sub-circuits. Interconnection of sub-circuits which are not adjacent on an integrated circuit substrate requires long conductors to be fabricated on the integrated circuit. Integrated circuits are becoming larger and the distance separating sub-circuits is increasing. When the distance from a driving transistor within a central buffer to a receiving transistor of a sub-circuit becomes long enough to adversely effect a signal's characteristics and propagation time, the interconnecting wire can be referred to as a "long wire".
Clock signals within integrated circuits are utilized to control the movement of data and synchronize control signals. Large designs require many different circuits to be synchronized and operate at the same speed. In such systems, a high frequency clock signal must be distributed over a large chip area. Currently, attempts to distribute clock signals in the range of one gigahertz are faltering due to the parasitic properties of long wires and long wire terminations.
A single source transistor driving many sink transistors creates a "fan-out" topology. Fanout circuits are commonly referred to as a "tree structure" or a "fanout tree". A fanout tree has detrimental loading characteristics on a propagating signal. This is particularly apparent when one "branch" of a fanout tree becomes more populated or more heavily loaded than another "branch".
The intermix of capacitance and resistance in a fanout tree creates a resistive-capacitive (R-C) time constant. A resistive capacitive time constant is a parasitic phenomena that retards the propagation of a signal and distorts the original form of the clock signal from its desired shape. A major factor in reducing propagation speed of a clock signal is the resistive effects of long wires in conjunction with the capacitance of a terminating transistor.
The resistance (R) of a wire increases linearly as a function of wire length (l) and, the resistance per unit length (r) of the material utilized, where R=rl. Likewise, the capacitance of a wire (C) increases linearly with its length (l) and capacitance per unit length (c). Capacitance can be defined by C=cl. The "R-C" delay (D) of a wire due to resistance and capacitances is D=(1/2)rcl.sup.2. As depicted by the l.sup.2 term, the delay due to the capacitive and resistive effects increases quadratically with the length of a wire. As clock speeds and the scale of integrated circuits continues to increase, timing difficulties associated with wire lengths have become a vexing problem.
In designing an integrated circuit, the physical layout is accomplished in view of all the pertinent design constraints. Generally, after the layout or geographical planning of a semiconductor chip is complete, circuit synchronization problems remain. Development of faster and larger integrated circuits has created the need for effective and efficient clock distribution networks, which do not require considerable effort to attain acceptable results after layout is complete.
Computer aided design tools can suggest potential problems such as unacceptable delays, but hundreds of variables must be assimilated. Best guess estimates are then utilized to solve synchronization difficulties. The propagation delay of a signal, due to long wires and multiple sinks, can be reduced by "repowering" or relaying the signal utilizing simple amplifiers, called buffers. However, buffers introduce uncertainties in the timing of integrated circuits and require chip area. Further, the effective insertion of buffers requires expensive computer design tools. Computer design tools merely estimate solutions and provide suggestions. Buffer solutions provide a less than perfect response for a marginal design topologies.
An area of integrated circuit design which has received additional attention recently is the area of providing solutions for unacceptable delays in high frequency digital circuits. Consumer demand for faster processing and higher clock frequencies has intensified the effort to find a solution for synchronization problems associated with clock signal distribution and clock signal delays.
A typical clock distribution network has hundreds of receiving circuits which are generally referred to as terminations or sinks. Terminations are typically realized by the gate of a metallic oxide semiconducting (MOS) transistor. Although each sink or receiving transistor has a relatively small R-C time constant, the cumulative effect of many sinks create excessive delays in clock signal propagation. Currently, designers of digital circuits are striving for a clock frequency of one gigahertz and higher. Therefore, implementation of an optimum clock distribution system has become critical to minimize delays and ensure synchronization. Rapid advances in transistor technology has reduced delay problems associated with transistor switching, but the transmission lines interconnecting the transistors have become the limiting factor for implementing increased clock speeds.
Currently, circuits having large R-C time constraints require the insertion of multiple buffers into the circuit to effectively decouple the R-C load. As integrated circuits become larger and chip area becomes cheaper, high frequency operation has been the focus of integrated circuit designers. Efforts to increase the clock speeds of digital circuits have revealed the importance and need for effective integrated circuit clock distribution systems.
Attenuation of a clock signal within an integrated circuit is defined by many factors. The attenuation of a clock signal within a clock distribution network is directly proportional to the square root of number of fan-outs.
The attenuation of the clock signal is inversely proportional to the physical properties of the transmission line. The attenuation of a transmission line is defined by EQU .alpha.=exp[-R/(2L/C]
Where R is the total resistance of the transmission line from the central clock buffer to the final destination, L is the total inductance of the transmission line and C is the capacitance of the transmission line.
As the attenuation of the transmission line increases, the clock signal power level at transmission line terminations decreases. Transmission line attenuation can be very high in present systems. A sub-circuit receiving a weak clock signal can cause serious design difficulties.
Typically, a specified amount of time after the estimated receipt of the leading edge of a clock signal, data transfer is accomplished within the integrated circuit. Many prior art methods for clock distribution are plagued by distortions or delays on the rising edge of the clock signal. If the rising edge is too late, the data transfer does not occur as required.
It should therefore be apparent that it would be advantageous to provide an integrated circuit clock distribution system which distributes an acceptable clock signal at very high clock speeds and requires minimal design rectifications.